Routing design specific global on chip wires for system-on-chip (SOCs) can be costly and inefficient. Instead, on-chip routers have been developed to route packets. Network-on-chip (NOC) routers route packets of data to and from desired locations on an integrated circuit. The performance of NOC routers depends on the communication infrastructure built into the chip. Latency and throughput define the performance of an NOC router, and high performance NOC routers look to achieve low power consumption, high data rates, and minimal area usage.
Various router designs including both synchronous and asynchronous designs have been explored for network-on-chip (NOC) applications. Routing algorithms such as wormhole, virtual channel, etc., have also been extensively studied. While asynchronous routers are expected to perform better than synchronous routers in NOC applications, the design of asynchronous routers is far more complicated than the design of synchronous routers.
One the other hand, a wormhole routing algorithm, where a chain of data (also called flits) propagates through the network like a worm when a path is available, is easy to implement compared to a virtual channel router, but is less efficient than the latter under congestion conditions, and consequently reduces throughput.
In virtual channel routing, during congestion, the entire data chain (packet) needs to be stored inside a router to clear the channel for other incoming packets and hence, virtual channel routing is complicated to design and requires larger storage space. This additional storage space can increase power consumption and require more area on the chip. Further, various lengths and types of buffer implementations have been explored to store data inside a router. However, to maximize the network performance in terms of latency and throughput, these techniques need to be optimized through better designs and implementations.